1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a flash memory device and a method of manufacturing the same.
2. Description of Related Art
Interest in flash memory devices as nonvolatile memory semiconductor devices has increased recently. A flash memory device uses a floating gate as a charge trapping layer. A proposed flash cell structure includes a split gate in which the width of a floating gate is narrower than that of a control gate disposed on the floating gate.
Such a split gate structure is constructed in a manner such that a charge trapping layer is only defined in a prescribed region below a control gate for the purpose of lowering power dissipation during programming and erasing operations while increasing programming and erasing efficiency. A flash memory device having this structure is formed such that the control gate and charge trapping layer only overlap along a partially defined length.
Problems occurring when manufacturing a typical split gate type flash memory cell will be described with reference to FIG. 1.
FIG. 1 is a sectional view of a flash memory device.
Referring to FIG. 1, a tunnel oxidation layer 21 is formed on a silicon semiconductor substrate 10, and a floating gate 31 is formed as a partially-defined charge trapping layer. An insulating cap layer 23 is formed on the floating gate 31, an oxide-nitride-oxide (ONO) layer 25 is formed on the insulating cap layer 23, and a control gate 35 is formed on the ONO layer 25. The ONO layer 25 acts as an interlayer insulating layer. A source/drain region 40 may be disposed between the floating gates 31.
When forming the flash memory device of split gate of FIG. 1, lengths L1 and L2 of the regions where the ONO layer 25 and the control gate 35 overlap may differ in a first cell and a second cell because of misalignment during a photolithography process. The photolithography process is performed while patterning the control gate 35. Misalignment between the control gate 35 and the underlying floating gate 31 may occur due to a loading effect that can occur during a photolithography process and a misalignment in the photolithography process.
The misalignment induces undesirable characteristic differences between neighboring cells. The misalignment results in different effective lengths of the control gate 35 and the floating gate 31, i.e., the charge trapping layers, in cells. Consequently, the characteristics of the cells are inconsistent.
When forming the floating gate 31 of the flash memory cell, a patterning etch step involving the use of a photoresist pattern is utilized. Here, an edge rounding effect impedes formation of the floating gate 31 with a small dimension.
Therefore, a flash memory device with a structure that can be manufactured without being influenced by photolithography equipment utilized during the photolithography process is needed. More specifically, to effectively and continuously reduce cell size in flash memory devices, a technique capable of preventing the misalignment caused by the photolithography process is needed.